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Jeff Draper
University of Southern California
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draper
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Home page:
http://www.isi.edu/~draper
Bio:
Dr. Jeff Draper holds a joint appointment as a Research Associate Professor in the Ming Hsieh Department of Electrical Engineering and Project Leader at Information Sciences Institute in the Viterbi School of Engineering at the University of Southern California. Dr. Draper has led the VLSI effort on several large programs in the past 14 years, including DARPA programs such as Trust in Integrated Circuits, Radiation Hardening by Design, Polymorphous Computing Architectures, and Data-Intensive Systems. In the past few years, his research group has fabricated several chips in IBM 90nm technology, including FPU processor test articles and two radiation-tolerant SRAM chips. Additionally, his group contributed to the architecture and VLSI implementation of the MONARCH chip in IBM 90nm technology, a 100M-gate chip containing 6 RISC processors with multimedia extension units, 12 MB of embedded DRAM, a streaming computing fabric, two external DDR DRAM memory ports, two Rapid I/O ports, and sixteen high-speed serial ports. This combination of elements of-fers over 64 GFLOPS of computing throughput, 60 GB/s of memory bandwidth, and 43 GB/s of off-chip bandwidth. Prior to this work, Dr. Draper's group completed the design and implementation of two generations of processing-in-memory (PIM) chips for the Data-Intensive Architecture (DIVA) project, with each chip containing on the order of 56 million transistors using TSMC 0.18-micron technology. Dr. Draper received a BS in Electrical Engineering from Texas A & M University and an MSE and PhD in Computer Engineering from the University of Texas at Austin. He has published over 70 papers on many aspects of VLSI and computer architecture. He has supervised the graduate research of over 20 students, with 9 students attaining PhDs. His research interests are resilience; Exascale architectures; memory-oriented architectures; radiation hardening by design; and interconnection networks, including networks on chip. Dr. Draper is an IEEE Senior Member.
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